1. Field of the Invention
The present invention generally relates to PLL frequency synthesizers, and, more particularly, to a method of controlling a phase comparator for performing a power saving operation and a semiconductor circuit.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional PLL frequency synthesizer. The PLL frequency synthesizer comprises a voltage control oscillator 102, a phase comparator unit 101, a low pass filter 106, and a microcomputer 108. The phase comparator unit 101 receives a comparison signal through an input terminal Fin and a reference signal through an input terminal OSCin. A capacitor 105 removes the DC component from the output of the voltage control oscillator 102 to obtain the comparison signal. A capacitor 104 removes the DC component from a reference frequency signal 103 to obtain the reference signal. The frequencies of the comparison signal and the reference signal are divided at respective frequency dividing rates, and the phases of both signals are compared. The phase comparator unit 101 then outputs through an output terminal Do a signal representing the phase difference between the comparison signal and the reference signal. The low pass filter 106 removes the high-frequency component from the phase difference signal and then inputs the phase difference signal into the voltage control oscillator 102 so as to control the oscillation frequency of the voltage control oscillator 102. The output signal 107 of the PLL frequency synthesizer is the output signal of the voltage control oscillator 102. The frequency of the output signal 107 can be varied at will by varying the frequency dividing rates inputted from the microcomputer 108 into the phase comparator unit 101 through its input terminals CLK, DT, and LE.
FIG. 2 is a block diagram of the phase comparator unit 101 of the conventional PLL frequency synthesizer of FIG. 1. The phase comparator unit 101 comprises a reference signal frequency dividing unit 202, a frequency divider 204, a comparison signal frequency dividing unit 205, a phase comparator 208, a charge pump 209, a power saving operation control circuit 212, and a control circuit 213. A reference signal 221 is inputted into a reference counter 203 of the reference signal frequency dividing unit 202 via an input buffer 201. After the frequency of the reference signal 221 is divided at a predetermined frequency dividing rate, the reference signal frequency dividing unit 202 supplies the divided reference signal to one of two input terminals of the phase comparator 208. After the frequency divider 204 divides the frequency of a comparison signal 222 at a predetermined frequency dividing rate, the comparison signal 222 is inputted into a swallow counter 206 and a main counter 207 of the comparison signal frequency dividing unit 205. The frequency of the comparison signal 222 is then divided again at a predetermined frequency dividing rate, and is inputted into the other input terminal of the phase comparator 208. The phase comparator 208 compares the phases of the two signals, and in accordance with the phase difference, outputs a phase difference signal 227 through the charge pump 209 and the output terminal Do. The output of the phase comparator 208 is also inputted into a digital lock detector 210, so that a lock signal 228 representing the phase synchronization state of the PLL frequency synthesizer is outputted through an LD terminal. An output select circuit 211, under the control of the control circuit 213, selects a monitor signal 229 from the two signals inputted into the phase comparator 208, and outputs the monitor signal 229 through an Fout terminal. The power saving operation control circuit 212 receives the output signal of the input buffer 201 and the output signal of the frequency divider 204, and controls the power saving operations of the reference signal frequency dividing unit 202, the comparison signal frequency dividing unit 205, the phase comparator 208, and the digital lock detector 210.
FIG. 3 is a timing chart of signals inputted into the control circuit 213. In this timing chart, Data DT is control data for controlling the phase comparator unit 101, and a clock CLK is a clock signal in synchronization with the bits of the data DT. The data DT is stored in the control circuit 213 only when a latch enable signal LE becomes high in synchronization with the clock CLK.
FIG. 4A shows an example structure of the control data inputted into the reference signal frequency dividing unit 202, and FIG. 4B shows an example structure of the control data inputted into the comparison signal frequency dividing unit 205. In both control data shown in FIGS. 4A and 4B, CN1 and CN2 indicate control bits for distinguishing between the control data for the reference signal frequency dividing unit 202 and the control data for the comparison signal frequency dividing unit 205. In FIG. 4A, bits 3, 4, 19, 20, 21, 22, and 23, each marked with ×, are dummy bits. In FIG. 4B, a bit 5 marked with × is a dummy bit. Both control data shown in FIGS. 4A and 4B are inputted one bit at a time, starting from the uppermost bit 23, at the timing shown in FIG. 3.
FIG. 5 shows the contents of the control bits CN1 and CN2. When both control bits CN1 and CN2 are “0”, the bits 3 to 23 represent the control data for the reference signal frequency dividing unit 202. When the control bit CN1 is “0” and the control bit CN2 is “1”, the bits 3 to 23 represent the control data for the comparison signal frequency dividing unit 205.
The bits 5 to 18 in FIG. 4A represent the control data for setting a frequency dividing rate “R” in the reference counter 203. The bits 6 to 12 in FIG. 4B represent the control data for setting a frequency dividing rate “A” in the swallow counter 206 of the comparison signal frequency dividing unit 205. The bits 13 to 23 in FIG. 4B represent the control data for setting a frequency dividing rate “N” in the main counter 207 of the comparison signal frequency dividing unit 205. The bit 4 in FIG. 4B represents the control data for setting a frequency dividing rate “P” in the frequency divider 204. Accordingly, the comparison signal frequency dividing unit 205 shown in FIG. 2 divides the frequency of a comparison signal at (P×N+A). The bit 3 in FIG. 4B represent control data for the digital lock detector 210 and the output select circuit 211.
FIG. 6 is a block diagram of the conventional power saving operation control circuit 212 shown in FIG. 2. A power saving restriction signal PSR is inputted into an inverter 601. When the power saving restriction signal PSR is low, a power saving operation is performed. When the power saving restriction signal PSR is high, the power saving operation is not performed. The output of the inverter 601 is inputted into an inverter 602. The output of the inverter 602 is inputted into one of the two input terminals of a NAND gate 603, the set terminal SET of a D-flip-flop 616, the reset terminal RESET of a D-flip-flop 617, and one of the two input terminals of a NAND gate 620 included in a set/reset flip-flop 621. NAND gates 619 and 620 constitute the set/reset flip-flop 621. An inverted signal XFPAR of the output signal of the frequency divider 204 is inputted into the D-input terminals of the D-flip-flops 616 and 617, and a first input terminal of a 3-input NAND gate 618. A reference signal FRAR is inputted into the other input terminal of the NAND gate 603.
Inverters 604-1 to 604-7 are cascaded, and the output terminal of the NAND gate 603 is connected to the input terminal of the inverter 604-1. The output terminal of the inverter 604-7 is connected to one of the two input terminals of a NAND gate 608. The output terminal of the NAND gate 608 is connected to the input terminal of an inverter 609, and the output terminal of the inverter 609 is connected to the input terminal of an inverter 610 and the clock input terminal CK of the D-flip-flop 616. The output terminal of the inverter 610 is connected to the inverted clock input terminal XCK of the D-flip-flop 616 and the input terminal of an inverter 611-1. Inverters 611-1 to 611-14 are cascaded, and the output of the inverter 611-14 is inputted into the input terminal of an inverter 615 and the inverted clock input terminal XCK of the D-flip-flop 617. The output of the inverter 615 is inputted into the clock input terminal CK of the D-flip-flop 617. The reset input terminal of the D-flip-flop 616 and the set input terminal of the D-flip-flop 617 are connected to a power source Vcc.
The inverted output XQ terminal of the D-flip-flop 616 is connected to a second input terminal of the 3-input NAND gate 618, and the output Q terminal of the D-flip-flop 617 is connected to a third input terminal of the 3-input NAND gate 618. The output of the 3-input NAND gate 618 is inputted into one of the two input terminals of the NAND gate 619 included in the set/reset flip-flop 621. The output of the NAND gate 620 included in the set/reset flip-flop 621 is inputted into the other input terminal of the NAND gate 608, the other input terminal of the NAND gate 619, and the input terminal of an inverter 622. The inverter 622 outputs an internal power saving restriction signal PSRS.
FIG. 7 is a timing chart of signals in the operation of the conventional power saving operation control circuit 212 of FIG. 6. When the power saving restriction signal PSR is low, the D-flip-flop 616 is set, the D-flip-flop 617 is reset, and the output of the NAND gate 620 is high. Ten gates after the reference signal FRAR rises as the power saving restriction signal PSR becomes high, the output CK1 of the inverter 609 rises from the low-level to the high-level. At the rise of the output CK1 of the inverter 609, the D-flip-flop 616 stores the inverted signal XFPAR of the output of the frequency divider 204, and outputs a high-level signal XQ1 through the inverted output terminal XQ. Sixteen gates after the rise of the output CK1 of the inverter 609, the output CK2 of the inverter 615 rises. At the rise of the output CK2, the D-flip-flop 617 stores the inverted signal XFPAR of the output of the frequency divider 204, and outputs a high-level signal Q2 through the output terminal Q. The output A of the 3-input NAND gate 618 becomes low, when the inverted signal XFPAR and the signals XQ1 and Q2 are all high. Accordingly, the output B of the NAND gate 619 becomes high, and the output C of the set/reset flip-flop 621 becomes low. As a result, the internal power saving restriction signal PSRS becomes high, thereby canceling the power saving state.
FIG. 8 is a flowchart of a power saving state canceling operation of the power saving operation control circuit 212. In step S1-1, the power saving restriction signal PSR rises to the high level. In step S1-2, it is determined whether the inverted signal XFPAR is high or low at the rise of the output signal CK1 of the inverter 609. If the inverted signal XFPAR is low, the operation moves on to step S1-3, in which it is determined whether the inverted signal XFPAR is high or low at the rise of the output signal CK2 of the inverter 615. If the inverted signal XFPAR is high, the operation moves on to step S1-4, in which the internal power saving state is canceled. In step S1-5, the power saving state is canceled in the reference counter 203 of the reference signal frequency dividing unit 202, the swallow counter 206 and the main counter 207 of the comparison signal-frequency dividing unit 205, and the phase comparator 208. The phase difference signal 227 is then outputted through the charge pump 209.
However, there are problems with the prior art described above. FIG. 9 illustrates a first problem of the power saving operation control circuit 212 of the prior art. The first problem is that a power saving state might be wrongly canceled due to noise. The noise is caused when a power saving state is canceled as the power saving restriction signal PSR is changes from the low level to the high level. The noise enters the reference signal FRAR and the inverted signal XFPAR of the output of the frequency divider 104. Because of this, the internal power saving restriction signal PSRS outputted from the power saving operation control circuit 212 becomes high, thereby promptly switching on the internal circuits of the phase comparator unit 101 including the reference signal frequency dividing unit 202, the comparator signal frequency dividing unit 205, and the phase comparator 208. As a result, the phases of the reference signal FRAR and the inverted signal XFPAR of the output of the frequency divider 204 are greatly shifted in relation to each other.
FIG. 10 illustrates a second problem of the power saving operation control circuit 121 of the prior art. The second problem is that, when the power saving restriction signal PSR changes from the low level to the high level to cancel a power saving state, the phase difference between the reference signal FRAR and the inverted signal XRPAR becomes constant. With the phase difference between the two signals being constant, the internal power saving restriction signal PSRS can never become high. As a result, the internal circuits of the phase comparator unit 101, including the reference signal frequency dividing unit 202, the comparison signal frequency dividing unit 205, and the phase comparator 208, are not actuated.